The present invention relates to semiconductor design technology, and more particularly, to an on-die termination circuit for generating a correct termination resistance that is rarely influenced by a variation of process, voltage and temperature (PVT)
Generally, various semiconductor devices manufactured as an integrated chip such as a central processing unit (CPU), a memory and a gate array are used in various electrical products such as a personal computer, a server and a workstation. Most of the semiconductor devices include a receiving circuit for receiving signals from the outside world through an input pad and an output circuit for outputting an internal signal to the outside world through an output pad.
As an operational speed of an electrical product is increased, a swing width of a signal interfaced among the semiconductor devices is decreased in order to minimize a delay time for transferring a signal. However, as the signal swing width is decreased, influence from external noise is increased and signal reflection due to impedance mismatching at an interface terminal is increased.
The impedance mismatching is caused by external noise or the PVT variation. When the impedance mismatching occurs, it is difficult to transfer data at high speed, and data output from an output terminal of the semiconductor device may be distorted. Therefore, when another semiconductor device receives the distorted data through an input terminal, a set-up/hold failure may occur or a level of the received data may be wrongly determined.
For solving the above-mentioned problem, the receiving semiconductor device which is operated at high speed includes an impedance matching circuit named an on-chip termination or an on-die termination near a pad in the integrated chip.
Generally, according to an on-die termination scheme, a source termination is performed by an output circuit at a transmitting device, and a parallel termination is performed by a termination circuit connected in parallel to a receiving circuit coupled to the input pad at a receiving device.
FIG. 1 is a block diagram showing a conventional on-die termination circuit.
As shown, the conventional on-die termination circuit includes a feedback unit 20, a comparison unit 30, a counting unit 40 and a control unit 10.
The feedback unit 20 receives an enable signal EN in order to output a level, of a code signal group P_CD<0:4> corresponding to an input-resistor ZQ, as a feedback signal P_FD. The comparison unit 30 detects a level difference between a reference voltage VREF and the feedback signal P_FD in response to the enable signal EN and a comparison enable signal LTCH_EN in order to output the detection result as a control signal CTRL.
The counting unit 40 up-counts or down-counts the code signal group P_CD<0:4> in response to the control signal CTRL. The control unit 10 repeatedly activates the enable signal EN and the comparison enable signal LTCH_EN in response to an initialization signal RST.
Herein, the control unit 10 includes a pulse signal generation unit 12, a completion timing indication unit 14 and an enable signal generation unit 16.
The pulse signal generation unit 12 generates a pulse signal CALP at regular intervals in response to the initialization signal RST. The completion timing indication unit 14 counts how many times the pulse signal CALP is activated in order to generate a completion signal CAL_STP.
The enable signal generation unit 16 repeatedly activates the enable signal EN and the comparison enable signal LTCH_EN in response to the pulse signal CALP and does not generate the enable signal EN and the comparison enable signal LTCH_EN in response to the completion signal CAL_STP.
Herein, the input-resistor ZQ is externally input through an input pin having a resistance of 240Ω between the input pad and a ground voltage. Further, the code signal group P_CD<0:4> has a level value of a binary code format. Furthermore, although not shown in FIG. 1, the on-die termination circuit includes a termination resistor supply unit for supplying a termination resistor to a data pad, wherein the termination resistor has a resistance which corresponds to the code signal group P_CD<0:4>.
FIG. 2 is a schematic circuit diagram illustrating the feedback unit 20 shown in FIG. 1.
As shown, the feedback unit 20 includes a signal input unit 22 for outputting the code signal group P_CD<0:4> as a selection signal group CD<0:4> in response to the enable signal EN; and a feedback signal supply unit 24 for outputting a voltage level of the selection signal group CD<0:4> corresponding to the input-resistor ZQ as the feedback signal P_FD.
In detail, the signal input unit 22 includes a plurality of NAND gates, each for receiving the enable signal EN and a corresponding one of the code signal group P_CD<0:4> in order to generate a corresponding one of the selection signal group CD<0:4>.
The feedback signal supply unit 24 includes a plurality of p-type metal oxide semiconductor (PMOS) transistors each of which has a gate that receives a corresponding one of the selection signal group CD<0:4> and each source is connected to a voltage VDDQ; a plurality of resistors each of which is connected between an output node and a drain of one of the plurality of PMOS transistors; and the input-resistor ZQ coupled to the output node in order to output a voltage loaded on the output node as the feedback signal P_FD.
An operation of the feedback unit 20 is described below.
When the enable signal EN is activated as a logic high level, the signal input unit 22 inverts the code signal group P_CD<0:4> to output the inverted signal as the selection signal group CD<0:4>.
Thereafter, one of the plurality of PMOS transistors is turned on in response to an activation of a corresponding one of the selection signal group CD<0:4> and thus a resistor coupled to one terminal of the active PMOS transistor is connected in parallel to the output node so that the feedback signal supply unit 24 outputs the feedback signal P_FD. That is, according to a resistance ratio between a pull-up resistor and the input-resistor ZQ, a voltage level of the feedback signal P_FD is determined. Herein, the pull-up resistor is formed because the resistor coupled to a drain of the active PMOS transistor is connected in parallel to the output node.
FIG. 3 is a wave diagram showing an operation of the conventional on-die termination circuit shown in FIGS. 1 and 2.
Referring to FIGS. 1 to 3, the operation of the conventional on-die termination circuit is described below.
When a semiconductor memory device is initially operated, as a voltage level of an external power supply voltage is stabilized, a power-up signal PWRUP is activated as a pulse form. At this time, the initialization signal RST is also activated.
Thereafter, the pulse signal generation unit 12 generates the pulse signal CALP at regular intervals in response to the initialization signal RST. The enable signal generation unit 16 activates the enable signal EN and the comparison enable signal LTCH_EN in response to each activation of the pulse signal CALP. Herein, while the enable signal EN is activated once, the comparison enable signal LTCH_EN is activated twice.
Thereafter, the feedback unit 20 outputs a level of the code signal group P_CD<0:4> corresponding to the input-resistor ZQ as the feedback signal P_FD in response to the enable signal EN. Thereafter, the comparison unit 30 detects a level difference between the reference voltage VREF and the feedback signal P_FD in response to the enable signal EN and the comparison enable signal LTCH_EN to output the control signal CTRL.
Thereafter, the counting unit 40 performs a down-counting operation or an up-counting operation based on a current version of the code signal group P_CD<0:4> according to the control signal CTRL in order to generate a new version of the code signal group P_CD<0:4>.
Meanwhile, when the feedback unit 20 is enabled once, the comparison unit 30 and the counting unit 40 are enabled twice because the comparison enable signal LTCH_EN is activated twice when the enable signal EN is activated once as above-mentioned.
Thereafter, the above-mentioned operation is performed ten times. Then, the enable signal generation unit 16 no more generates the enable signal EN and the comparison enable signal LTCH_EN as instructed by the completion timing indication unit 14.
That is, the completion timing indication unit 14 activates the completion signal CAL_STP when the pulse signal CALP is activated more than ten times. Thereafter, the enable signal generation unit 16 does not generate the enable signal EN and the comparison enable signal LTCH_EN, in response to the completion signal CAL_STP.
As a result, the conventional on-die termination circuit repeatedly performs the above-mentioned operations to adjust the feedback signal P_FD so that a voltage level of the feedback signal P_FD corresponds to the reference voltage VREF and, thus, a resistance of a termination resistor supplied by the code signal group P_CD<0:4> equals that of the input-resistor ZQ.
Herein, the reference voltage VREF has a voltage level of (½)*VDDQ. Therefore, the code signal group P_CD<0:4> is adjusted for the feedback signal P_FD to have the voltage level (½)*VDDQ.
However, according to the conventional on-die termination circuit, a termination resistor which corresponds to the input-resistor ZQ cannot be generated when the PVT variation occurs. Thus, a semiconductor memory device is abnormally operated.
FIG. 4 is a wave diagram showing a malfunction of the conventional on-die termination circuit due to the PVT variation. Particularly, a level variation of the feedback signal P_FD is shown when the enable signal EN is activated once.
Referring to FIG. 4, since the feedback unit 20 is enabled by the activation of the enable signal EN, a level of the feedback signal P_FD is developed by the pull-up resistor which corresponds to the code signal group P_CD<0:4> and the input-resistor ZQ.
However, at the timing point ‘a’ when the comparison enable signal LTCH_EN is firstly activated, the feedback signal P_FD is not completely developed to a level which corresponds to the pull-up resistor and the input-resistor ZQ. Accordingly, when the comparison enable signal LTCH_EN is firstly activated, the comparison unit 30 and the counting unit 40 receive the wrong feedback signal P_FD to be operated.
In detail, since the feedback signal P_FD is not completely developed at the first activation of the comparison enable signal LTCH_EN, the comparison unit 30 determines that a level of the feedback signal P_FD is low in comparison with the reference voltage VREF and, thus, outputs a signal of a logic low level. The counting unit 40 up-counts the code signal group P_CD<0:4> in response to the output signal of the comparison unit 30.
Thereafter, at a second activation timing of the comparison enable signal LTCH_EN, the level development of the feedback signal P_FD according to the pull-up resistor and the input-resistor ZQ is finished. Further, since the code signal group P_CD<0:4> is up-counted at the first activation timing, a level of the feedback signal P_FD is higher than the reference voltage VREF.
Therefore, the comparison unit 30 outputs a signal of a logic high level and the counting unit 40 down-counts the code signal group P_CD<0:4>. Accordingly, while the enable signal EN is activated once, the comparison unit 30 and the counting unit 40 up-count the code signal group P_CD<0:4> once and down-count the code signal group P_CD<0:4> once.
Since the conventional on-die termination circuit performs the above-mentioned operation ten times, the up-counting and the down-counting are repeatedly performed at each operation. As a result, the code signal group P_CD<0:4> is not changed substantially.
Herein, the development time of the feedback signal P_FD is varied according to a capacitance of a pad through which the input-resistor is input and a resistance of the pull-up resistor in the feedback unit. For instance, when the capacitance is large and the resistance is large, the development time is increased. Further, the development time is increased due to the PVT variation.
Meanwhile, since the conventional on-die termination circuit is abnormally operated due to the PVT variation, a termination resistor which corresponds to the input-resistor cannot be generated. Since the termination resistor is used for a semiconductor memory device to normally receive a command, an address and a data, a semiconductor memory device may be abnormally operated due to the wrong termination resistor.